ASIC/FPGA Design Engineer

As an ASIC Designer/Engineer (Hardware), you will be working within the Hardware Development Team designing, implementing and verifying complete customer products. This team works within a process framework that requires us to meet the objectives of processes such as DO-178B/DO-254 or ISO26262/ISO16949.  The role will include all aspects of product development such as creating robust and complete requirements, estimating design effort, researching and implementing various technologies to enhance GNSS positioning, doing detailed design tradeoffs, and performing verification activities. You will adhere and contribute to Hexagon A&P design best practices and necessary design processes. You will pro-actively interact with the rest of the development team to ensure that the design meets its, functional, safety, quality, schedule and cost targets.

The Location: Hexagon is a global company with offices around the world. This hybrid work from home and office position is based in Calgary, AB. 

As an ASIC Designer/Engineer (Hardware), responsibilities include: 

• ASIC/FPGA design from requirements capture to RTL, verification, tracing and final qualification of prototypes
• Work collaboratively with cross-functional disciplines to create an overall product that is cost effective while delivering industry-leading performance.
• Develop circuit designs in industry-standard tool flows and run associated simulations to verify performance parameters and signal/power integrity.
• Hardware design, prototyping, debugging and hardware verification throughout the product life cycle
• Create design documentation which includes conceptual ideas, design specifications, test plans and test results

Must-Have:  

• Bachelor of Science in Electrical Engineering from a four-year college or university program with 3-6 years experiance.
• Intimate knowledge of ASIC and or FPGA design flows covering all phases of the design cycle including architecture and design specification with strong skills in RTL logic design, coding in VHDL and Verilog, verification, synthesis, formal verification and static timing analysis.
• Experience with Mentor ModelSim for simulation and Synopsys design tools for static timing analysis and equivalence checking.
• Experience with cross clock domain designs, GNSS signal structures, ARM processors, AMBA, DMA, memory interfaces, and other IP is a huge asset.
• Experience in requirements definition and writing technical specifications.
• Excellent communication skills and team work abilities.

Nice-to-Have:

• Hands-on experience with chip bring-up, debug, and lab equipment such as logic analyzer and digital oscilloscopes.
• Some experience with one or more programming or scripting languages (C/C++, Perl, TCL, etc.).
• Previous experience in SOC design involving embedded processors (preferably ARM knowledge).
• Knowledge of GPS/GNSS.

Not sure if you meet all the qualifications for this role? Let us decide! At Hexagon, we are committed to a diverse and inclusive work environment. If you’re excited about the opportunities this role could bring, we encourage you to apply. For any questions about the role or our company, please email our team at hrrecruitingteam.ap@hexagon.com and we will be pleased to follow up with you. Please do not send cover letters or resumes to this address.

The Company: Hexagon is a global leader in digital reality solutions, combining sensor, software, and autonomous technologies. We are putting data to work to boost efficiency, productivity, quality, and safety across industrial, manufacturing, infrastructure, public sector, and mobility applications. You’ll be joining over 24,000 people in 50 countries on the leading edge of your field. 

This position is with Hexagon’s Autonomy & Positioning division, a global technology leader, pioneering end-to-end solutions for assured positioning and autonomy on land, sea, and air. Our work touches every aspect of life, from sustainability on Earth to enabling autonomy. Come see why we are recognized as one of Alberta's Top 75 Employers.